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fully accurate, 12 - /14 - /16 - bit v out nano dac, quad, spi interface, 4.5 v to 5.5 v in tssop data sheet ad5024 / ad5044 / ad5064 rev. f document feedback information furnis hed by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject t o change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2008 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features low power quad 12 - /14 - /16 - bit dac, 1 lsb inl pin compatible and performance upgrade to ad5666 individual and common voltage reference pin options rail - to - rail operation 4.5 v to 5.5 v power supply power - on reset to zero scale or midscale 3 power - down functions and per - channel power - down hardware ldac with software ldac override function clr function to programmable code sdo daisy - chaining option 14 -/ 16 - lead tssop internal reference buffer and internal output amplifier applications process control data acquisition systems portable battery - powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenu ators functional block dia grams 06803-064 interface logic and shift register input register din sdo ldac gnd v dd ldac v refin sync sclk ad5064-1 clr v out a v out b v out c v out d dac register dac a buffer input register dac register dac b buffer input register dac register dac c buffer input register dac register dac d buffer por power-down logic power-on reset figure 1 . ad5064 - 1 functional equivalent and pin compatible with ad5666 interface logic and shift register input register din ldac gnd v dd ldac v ref a sync sclk ad5024/ ad5044/ ad5064 clr v out a v out b v out c v out d dac register dac a buffer input register dac register dac b buffer input register dac register dac c buffer input register dac register dac d buffer v ref b v ref c v ref d por power-down logic power-on reset 06803-001 figure 2 . ad5024/ad5044/ad5064 with individual refere nce pins general description the ad5024 / ad5044 / ad5064 / ad5064 -1 are low p ower, quad 12- /14 - /16 - bit buffered voltage output nano dac? converters that offer relative accuracy specifications of 1 lsb inl and 1 lsb dnl with the ad5024/ad5044/ad5064 individual reference pin and the ad5064 - 1 common reference pin options. the ad5024/ad5044/ad5064/ad5064 -1 can operate from a single 4.5 v to 5.5 v supply. the ad5024/ad5044/ad5064/ad5064 - 1 also offer a differen tial accuracy specification of 1 lsb. the parts use a versatile 3 - wire, low power schmitt trigger serial interface that operates at clock rates up to 50 mhz and is compati - ble with standard spi, qspi?, microwire?, and dsp interface standards. integrated refe rence buffers and output amplifiers are also provided on - chip. the ad5024/ad5044/ad5064/ad5064 - 1 incor porate a power - on reset circuit that ensures the dac output powers up to zero scale or midscale and remains there until a valid write takes place to the device. the ad5024/ad5044/ ad5064/ad5064 - 1 contain a power - down feature that reduces the current consumption of the device to t ypically 400 na at 5 v and provides software selectable output loads while in power - down mode. total unadjusted error for the parts is <2 mv. product highlights 1. quad channel available in 14 - /16 - lead tssop packages. 2. 16- bit accurate, 1 lsb inl. 3. high speed serial interface with cl ock speeds up to 50 mhz. 4. reset to known output voltage (zero scale or midscale). table 1 . related devices part no. description ad5666 quad,16 - bit buffered dac, 16 lsb inl, tssop ad5025 / ad5045 / ad5065 dual, 16 - bit buffered dacs, 1 lsb inl, tssop ad5062 , ad5063 16- bit nano dac, 1 lsb inl, sot - 23, msop ad5061 16- bit nano dac, 4 lsb inl, sot -23 ad5040 / AD5060 14 - /16 - bit nano dac, 1 lsb inl, sot -23
ad5024/ad5044/ad5064 data sheet rev. f | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagrams ............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ac characteristics ........................................................................ 4 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 7 esd caution .................................................................................. 7 pin configurations and function descriptions ........................... 8 typical performance characteristics ........................................... 10 terminology .................................................................................... 17 theory of operation ...................................................................... 19 digital - to - analog converter .................................................... 19 dac architecture ....................................................................... 19 reference buffer ......................................................................... 19 output amplifier ........................................................................ 19 serial interface ............................................................................ 19 shift register ............................................................................... 19 modes of operation ................................................................... 21 power - on reset .......................................................................... 22 power - down modes .................................................................. 22 clear code register ................................................................... 23 ldac function .......................................................................... 23 power supply bypassing and grounding ................................ 24 microprocessor interfacing ....................................................... 25 applications information .............................................................. 26 using a reference as a power supply ....................................... 26 bipolar opera tion ....................................................................... 26 using the ad5024/ad5044/ad5064/ad5064 - 1 with a galvanically isolated interface ................................................. 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 28 revision history 6/13 rev. e to rev. f change to standalone mode section ........................................... 21 5/ 11 rev. d to rev. e changes to table 4 ............................................................................ 5 change s to figure 4 and figure 5 ................................................... 6 8/10 rev. c to rev. d change to minimum sync high time (single channel update) parameter, table 4 ............................................................. 5 5/10 rev. b to rev. c changes to power - on reset section ............................................ 22 6 /09 rev. a to rev. b changes to figure 1 .......................................................................... 1 3/09 rev. 0 to rev. a adde d 14 - lead tssop ...................................................... universal added figure 1; renumbered sequentially .................................. 1 changes to features section, general description section, product highlights section, figure 2, and table 1 ....................... 1 changes to table 2 ............................................................................ 3 changes to timing characteristics section and table 4 ............. 5 a dded circuit and timing diagrams section and figure 3 ....... 5 added figure 5 ................................................................................... 6 changes to figure 4 ........................................................................... 6 added figure 6 ................................................................................... 8 added table 6; renumbered sequentially ..................................... 8 changed input shift register to shift register throughout ....... 8 changes to table 7 ............................................................................. 9 changes to typical per formance characteristics section ........ 10 changes to terminology section ................................................. 17 changes to digital - to - analog converter section, reference buffer section, output amplifier section, serial interface section, shift register section, and table 8 ................................ 19 changes to figure 47, figure 48, and figure 49 captions ........ 20 added modes of operation section, daisy - chaining section, table 10, and table 11 .................................................................... 21 changes to table 13 and power - down mode section .............. 22 changes to table 16 ....................................................................... 24 changes to figure 52 to figure 55 ................................................ 25 changes to bipolar oper ation section and figure 56 to figure 58 .......................................................................................... 26 added figure 59 ............................................................................. 27 updated outline dimensions ....................................................... 27 changes to ordering guide .......................................................... 28 8/08 revision 0: initial version
data sheet ad5024/ad5044/ad5064 rev. f | page 3 of 28 specifications v dd = 4.5 v to 5.5 v, r l = 5 k? to gnd, c l = 200 pf to gnd, 2.5 v v refin v dd , unless otherwise specified. all specifications t min to t max , unless otherwise noted. table 2 . parameter b grade 1 a grade 1 , 2 unit conditi ons/comments min typ max min typ max static performance 3 resolution 16 16 bits ad5064/ad5064 -1 14 bits ad5044 12 bits ad5024 relative accuracy (inl) 4 0.5 1 0.5 4 lsb ad5064/ad5064 - 1; t a = ?40c to +105c 0.5 2 0.5 4 lsb ad5064/ad5064 - 1; t a = ?40c to +125c 0.25 1 lsb ad5044 0.12 0.5 lsb ad5024 differential nonlinearity (dnl) 4 0.2 1 0.2 1 lsb total unadjusted error 2 2 mv v ref = 2.5 v, v dd = 5.5 v offset error 4 , 5 0.2 1.8 0.2 1.8 mv offset error temperature coefficient 4 , 6 2 2 v/c full - scale error 4 0.01 0.07 0.01 0.07 % fsr all 1s loaded to dac register, v ref < v dd gain error 4 0.005 0.05 0.005 0.05 % fsr v ref < v dd gain temperature coefficient 4 , 6 1 1 ppm fsr/c dc cro sstalk 4 , 6 40 40 v due to single - channel, full - scale output change, r l = 5 k? to gnd or v dd 40 40 v/ma due to load current change 40 40 v due to powering down (per channe l) output characteristics 6 output voltage range 0 v dd 0 v dd v capacitive load stability 1 1 nf r l = 5 k ?, r l = 100 k?, and r l = dc output impedance normal mode 0.5 0.5 ? power - down mode output connected to 100 k ? netw ork 100 100 k ? outpu t impedance tolerance 20 k ? output connected to 1 k ? netwo rk 1 1 k ? outpu t impedance tolerance 400 ? short- circuit current 60 60 ma dac = full scale, output shorted to gnd 45 45 ma dac = zero scale, output shorted to v dd power - up time 7 4.5 4.5 s dc psrr ?92 ?92 db v dd 10%, dac = full scale, v ref < v dd reference inputs reference input range 2.2 v dd 2.2 v dd v reference current 35 50 35 50 a per dac channel; individual reference option 140 160 140 160 a single reference option reference input impedance 120 120 k? individual reference option 32 32 k? single reference option logic inputs input current 8 1 1 a input low voltage, v inl 0.8 0.8 v input high voltage, v inh 2.2 2.2 v pin capacitance 6 4 4 pf
ad5024/ad5044/ad5064 data sheet rev. f | page 4 of 28 parameter b grade 1 a grade 1 , 2 unit conditi ons/comments min typ max min typ max logic outputs (sdo) 9 output low voltage, v ol 0.4 0.4 v i sink = 2 ma output high voltage, v oh v dd ? 1 v dd ? 1 i source = 2 ma high impedance leakage current 0.002 1 0.002 1 a high impedance output capacitance 6 7 7 pf power requirements v dd 4.5 5.5 4.5 5.5 v dac active, excludes load current i dd 10 v ih = v dd , v il = gnd, code = midscale normal mode 4 6 4 6 ma all power - down modes 11 0.4 2 0.4 2 a t a = ?40c to +105c 30 30 a t a = ?40c to +125c 1 temperature range is ?40c to +125c, typical at 25c. 2 a grade offered in ad5064 only. 3 linearity and total unadjusted error are calculated using a reduced code range ad5064/ad5064 - 1: code 512 to code 65,024; ad5044: code 128 to code 16,256; ad5024: code 32 to code 4064. output unloaded. 4 see the terminology section. 5 offset error calculated using a reduced code range ad5064/ad5064- 1: code 512 to code 65,024; ad5044: code 128 to code 16,256; ad5024: code 32 to code 4064. output unloaded 6 guaranteed by design and characterization; not production tested. 7 time to exit power - down mode to normal mode; 32 nd clock edge to 90% of dac midscale value, output unloaded. 8 current flowing into individual digital pins. v dd = 5.5 v; v ref = 4.096 v; code = midscale. 9 ad5064 - 1 only. 10 interface inactive. all dacs active. dac outputs unloaded . 11 all four dacs powered down . ac characteristics v dd = 4.5 v to 5.5 v, r l = 5 k? to gnd, c l = 200 pf to gnd, 2.5 v v refin v dd . all specifications t min to t max , unless otherwise noted. table 3. parameter 1 , 2 min typ max unit conditions/comments 3 output voltage settling time 5.8 8 s ? to ? scale and ? to ? scale settling to 1 lsb, r l = 5 k?, single - channel update 10.7 13 s ? to ? scale and ? to ? scale settling to 1 lsb, r l = 5 k?, all channel update slew rate 1.5 v/s digital -to - analog glitch impulse 3 nv - sec 1 lsb change around major carry reference feedthrough ?90 db v ref = 3 v 0.86 v p - p, frequency = 100 hz to 100 khz digital feedthrough 0.1 nv - sec digital crosstalk 1.9 nv - sec analog crosstalk 2 nv - sec dac -to - dac crosstalk 3.5 nv - sec ac crosstalk 6 nv - sec multiplying bandwidth 340 khz v ref = 3 v 0.86 v p -p total harmonic distortion ?80 db v ref = 3 v 0.2 v p - p, frequency = 10 khz output noise spectral density 64 nv/ hz dac code = 0x8400, frequency = 1 khz 60 nv/ hz dac code = 0x8400, frequency = 10 khz output noise 6 v p -p 0.1 hz to 10 hz 1 guaranteed by design and characterization; not production tested. 2 see the terminology section. 3 temperature range is ?40c to +125c, typical at 25c.
data sheet ad5024/ad5044/ad5064 rev. f | page 5 of 28 timing characteristi cs all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. see figure 4 and figure 5 . v dd = 4.5 v to 5.5 v. all specifications t min to t max , unle ss otherwise noted. table 4. parameter 1 symbol min typ max unit sclk cycle time t 1 20 ns sclk high time t 2 10 ns sclk low time t 3 10 ns sync to sclk falling edge setup time t 4 17 ns da ta setup time t 5 5 ns data hold time t 6 5 ns sclk falling edge to sync rising edge t 7 5 30 ns minimum sync high time (single channel update) t 8 3 s minimum sync h igh time (all channel update) t 8 8 s sync rising edge to sclk fall ignore t 9 17 ns ldac pulse width low t 10 20 ns sclk falling edge to ldac rising edge t 11 20 ns clr minimum pulse width low t 12 10 ns sclk falling edge to ldac falling edge t 13 10 ns clr pulse activation time t 14 10.6 s sclk rising edge to sdo valid t 15 2 , 3 22 ns sclk falling edge to sync rising edge t 16 2 5 ns sync rising edge to sclk rising edge t 17 2 8 ns sync rising edge to ldac / clr falling edge (single channel update) t 18 2 2 s sync rising edge to ldac / clr falling edge (all channel update) t 18 2 8 s power - up time 4 4.5 s 1 maximum sclk frequency is 50 mhz at v dd = 4.5 v to 5.5 v. guaranteed by design and characterization; not production tested. 2 daisy - chain mode only. 3 measured with the load circuit of figure 3 . t 15 determines the maximum sclk frequency in daisy - chain mode. ad5064 - 1 only. 4 time to exit power - down mode to normal mode of ad5024/ad5044/ad5064/ad5064 -1 , 32 nd clock edge to 90% of dac midscale valu e, with output unloaded. circuit and timing diagrams 2m a i ol 2m a i oh t o output pin c l 50pf 06803-002 2 v oh (min) + v ol (max) figure 3 . load circuit for digital output (sdo) timing specifications
ad5024/ad5044/ad5064 data sheet rev. f | page 6 of 28 t 4 t 3 sclk sync din t 1 t 2 t 5 t 6 t 7 t 8 db31 t 9 t 10 t 11 ldac 1 ldac 2 t 13 1 asynchronous ldac update mode. 2 synchronous ldac update mode. clr t 12 t 14 v out db0 06803-003 figure 4. serial write operation t 8 t 4 t 6 t 15 t 18 t 16 t 17 t 10 t 5 32 64 sclk sync din sdo undefined input word for dac n input word for dac n input word for dac n + 1 db0 db31 db0 db31 db31 db0 t 18 t 12 06803-004 ldac 1 1 if in daisy-chain mode, ldac must be used asynchronously. clr figure 5. daisy-chain timing diagram
data sheet ad5024/ad5044/ad5064 rev. f | page 7 of 28 absolute maximum rat ings t a = 25c, unless otherwise noted. table 5. parameter rating v dd to gnd ?0.3 v to +7 v digital input voltage to gnd ?0.3 v to v dd + 0.3 v v out to gnd ?0.3 v to v dd + 0.3 v v ref to gnd ?0.3 v to v dd + 0.3 v operating temperature range industrial ?40c to +125c storage temperature range ?65c to +150c junction temperature (t j max ) 150c tssop package pow er dissipation (t j max ? t a )/ ja ja thermal impedance 113c/w reflow soldering peak temperature pb - free 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functio nal operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caut ion
ad5024/ad5044/ad5064 data sheet rev. f | page 8 of 28 pin configurations and function descriptions por v out c v out a v refin din gnd v out b v out d sdo sclk clr v dd ldac sync top view (not to scale) 1 2 3 4 5 6 7 ad5064-1 14 13 12 11 10 9 8 0 6803-065 figure 6. 14-lead tssop (ru-14) table 6. pin function descriptions pin no. mnemonic description 1 ldac ldac can be operated in two modes, asynchronously and synchronously, as shown in figure 4. pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows all dac outputs to simultaneously update. this pin can also be tied permanently low in standalone mode. when daisy-chain mode is enabled, this pi n cannot be tied permanently low; the ldac pin should be used in asynchronous ldac update mode, as shown in figure 5, and the ldac pin must be brought high after pulsing. 2 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it powers on the sclk and din buffers and enables the shift register. data is transferred in on the falling edges of the next 32 clocks. if sync is taken high before the 32 nd falling edge, the rising edge of sync acts as an interrupt and the write sequence is ignored by the device. 3 v dd power supply input. these parts can be operated from 4.5 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 v out a analog output voltage from dac a. the outp ut amplifier has rail-to-rail operation. 5 v out c analog output voltage from dac c. the outp ut amplifier has rail-to-rail operation. 6 por power-on reset pin. tying this pin to gnd powers up all four dacs to zero scale. tying this pin to v dd powers up all four dacs to midscale. 7 v refin this is a common pin for reference input for dac a, dac b, dac c, and dac d. 8 sdo serial data output. can be used to daisy-chain a number of ad5064-1 devices together. the serial data is transferred on the rising edge of sclk an d is valid on the falling edge of the clock. 9 clr asynchronous clear input. the clr input is falling edge sensitive. when clr is low, all ldac pulses are ignored. when clr is activated, the input register and the dac register are updated with the data contained in the clear code registerzero, midscale, or full scale. default setting clears the output to 0 v. 10 v out d analog output voltage from dac d. the outp ut amplifier has rail-to-rail operation. 11 v out b analog output voltage from dac b. the outp ut amplifier has rail-to-rail operation. 12 gnd ground reference point for all circuitry on the part. 13 din serial data input. this device has a 32-bit shift regi ster. data is clocked into the shift register on the falling edge of the serial clock input. 14 sclk serial clock input. data is clocked into the shift register on the falling edge of the serial clock input. data can be transferred at rates of up to 50 mhz.
data sheet ad5024/ad5044/ad5064 rev. f | page 9 of 28 v out a v ref a v ref b v out c por din gnd v out b v out d v ref c v ref d sclk clr v dd ldac sync top view (not to scale) 1 2 3 4 5 6 7 8 ad 5024/ ad 5044/ ad5064 16 15 14 13 12 11 10 9 06803-005 figure 7 . 16 - lead tssop (ru - 16) pin configuration table 7 . pin function descriptions pin no. mnemonic desc ription 1 ldac ldac can be operated in two modes, asynchronously and synchronously, as shown in figure 4 . pulsing this pin low allows any or all dac registers to be updated i f the input registers have new data. this allows all dac outputs to simultaneously update. this pin can also be tied permanently low in standalone mode. 2 sync active low control input. this is the frame synchronization signal for the i nput data. when sync goes low, it powers on the sclk and din buffers and enables the shift register. data is transferred in on the falling edges of the next 32 clocks. if sync is taken high before the 32 nd falling edge , the rising edge of sync acts as an interrupt and the write sequence is ignored by the device. 3 v dd power supply input. these parts can be operated from 4.5 v to 5.5 v, and the supply should be decoupled with a 10 f capacitor in para llel with a 0.1 f capacitor to gnd. 4 v ref b dac b reference input. this is the reference voltage input pin for dac b. 5 v ref a dac a reference input. this is the reference voltage input pin for dac a. 6 v out a analog output voltage from dac a. the output amplifier has rail -to - rail operation. 7 v out c analog output voltage from dac c. the output amplifier has rail -to - rail operation. 8 por power - on reset. tying this pin to gnd powers up the part to 0 v. tying this pin to v dd powers up the part to midscale. 9 v ref c dac c reference input. this is the reference voltage input pin for dac c. 10 clr asynchronous clear input. the clr input is falling edge sensitive. when clr is low, all ldac pulses are ignored. when clr is activated, the input register and the dac register are updated with the data contained in the clear code register zero, midscale, or full scale. default setting clears the output to 0 v. 11 v ref d dac d re ference input. this is the reference voltage input pin for dac d. 12 v out d analog output voltage from dac d. the output amplifier has rail -to - rail operation. 13 v out b analog output voltage from dac b. the output amplifier has rail -to - rail operation. 14 gnd ground reference point for all circuitry on the part. 15 din serial data input. this device has a 32 - bit shift register. data is clocked into the shift register on the falling edge of the serial clock input. 16 sclk serial clock input. data is clocke d into the shift register on the falling edge of the serial clock input. data can be transferred at rates of up to 50 mhz.
ad5024/ad5044/ad5064 data sheet rev. f | page 10 of 28 typical performance characteristics 1.0 0.2 0 ?0.6 ?1.0 512 16,640 32,768 48,896 65,024 06803-019 inl (lsb) dac code 0.8 0.6 0.4 ?0.4 ?0.2 ?0.8 v dd = 5v v ref = 4.096v t a = 25c figure 8 . ad5064/ad5064 - 1 inl 1.0 0.2 0 ?0.6 ?1.0 06803-020 inl (lsb) dac code 0.8 0.6 0.4 ?0.4 ?0.2 ?0.8 0 512 1024 1536 2048 2560 3072 3584 4096 v dd = 5v v ref = 4.096v t a = 25c figure 9 . ad5044 inl 1.0 0.2 0 ?0.6 ?1.0 06803-021 inl (lsb) dac code 0.8 0.6 0.4 ?0.4 ?0.2 ?0.8 0 512 1024 1536 2048 2560 3072 3584 4096 v dd = 5v v ref = 4.096v t a = 25c figure 10 . ad5024 inl 1.0 0.2 0 ?1.0 ?0.4 512 16,640 32,768 48,896 65,024 06803-022 dnl (lsb) dac code ?0.8 ?0.6 ?0.2 0.8 0.6 0.4 v dd = 5v v ref = 4.096v t a = 25c figure 11 . ad5064/ad5064 - 1 dnl 1.0 0.2 0 ?0.6 ?1.0 06803-023 dnl (lsb) dac code 0.8 0.6 0.4 ?0.4 ?0.2 ?0.8 0 4096 8192 12,288 16,384 v dd = 5v v ref = 4.096v t a = 25c figure 12 . ad5044 dnl 1.00 0 06803-024 dnl (lsb) dac code 0.75 0.50 0.25 ?1.00 ?0.75 ?0.50 ?0.25 0 4096 8192 12,288 16,384 v dd = 5v v ref = 4.096v t a = 25c figure 13 . ad5024 dnl
data sheet ad5024/ad5044/ad5064 rev. f | page 11 of 28 0.20 0.10 0 ?0.10 ?0.20 512 16,640 32,768 48,896 65,024 06803-025 tue (mv) dac code 0.15 ?0.05 0.05 ?0.15 v dd = 5v v ref = 4.096v t a = 25c figure 14 . total unadjusted error (tue) 06803-026 2.0 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 5.5 5.0 4.5 4.0 3.5 3.0 2.5 in l error (lsb) reference vo lt age (v) max in l error @ v dd = 5.5v min in l error @ v dd = 5.5v t a = 25c figure 15 . inl vs. reference input voltage 06803-027 2.0 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 5.5 5.0 4.5 4.0 3.5 3.0 2.5 dn l error (lsb) reference voltage (v) t a = 25c max dnl error @ v dd = 5.5v min dnl error @ v dd = 5.5v figure 16 . dnl vs. reference input voltage 06803-028 2.0 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 5.5 5.0 4.5 4.0 3.5 3.0 2.5 tue (mv) reference vo lt age (v) max tue @ v dd = 5.5v min tue @ v dd = 5.5v t a = 25 c figure 17 . tue vs. reference input volta ge 0.015 0.010 0.005 0 ?0.015 ?60 ?20 40 80 140 06803-029 gain error (%fsr) temperature (c) ?0.005 ?0.010 ?40 0 20 60 100 120 v dd = 5.5v v ref = 4.096v dac a dac b dac c dac d figure 18 . gain error vs. temperature dac a 0.6 0.4 0.3 0 ?0.4 ?60 0 40 80 140 06803-030 offset error (mv) temperature (oc) 0.5 0.2 0.1 ?0.1 ?0.2 ?0.3 ?40 20 ?20 60 100 120 dac c dac d dac b v dd = 5.5v v ref = 4.096v figure 19 . offset error vs. temperature
ad5024/ad5044/ad5064 data sheet rev. f | page 12 of 28 0.2 0.1 0 ?0.1 ?0.2 4.50 4.75 5.00 5.25 5.50 06803-031 error (%fsr) v dd (v) gain error full-scale error v ref = 4.096v t a = 25c figure 20 . gain error and full - scale error vs. supply voltage 0.12 0.09 0.06 0.03 0 4.50 4.75 5.00 5.25 5.50 06803-032 offset error (mv) v dd (v) v ref = 4.096v t a = 25c figure 21 . offset error voltage vs. supply voltage 06803-033 i dd power-up (ma) hits 3.9 4.0 4.1 4.2 4.3 0 5 10 15 20 25 30 35 40 mean: 4. 1 1699 sd: 0.0544403 limits: lo w : 3 high: 4.3 cpk: lo w : 6.84 high: 1.12 v ref = 4.096v t a = 25c code = midscale figure 22 . i dd histogram, v dd = 5.0 v 06803-034 0 2 4 6 8 10 0 10,000 20,000 30,000 40,000 50,000 60,000 70,000 dac code i dd (ma) v dd = 5.5v v ref = 4.096 t a = 25c figure 23 . supply current vs. code 06803-035 0 2 4 6 8 10 i dd (ma) temperature (c) v dd = 5.5v v ref = 4.096 code = midscale ?40 ?20 0 20 40 60 80 100 120 figure 24 . supply current vs. temperature 06803-036 supply vo lt age (v) i dd (ma) 0 2 4 6 8 10 v dd = 5.5v v ref = 4.096 t a = 25c 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 figure 25 . supply current vs. supply voltage
data sheet ad5024/ad5044/ad5064 rev. f | page 13 of 28 06803-037 digital input voltage (v) i dd (ma) 0 2 4 6 8 10 0 1 2 3 4 5 v dd = 5.5v v ref = 4.096 t a = 25c figure 26 . supply current vs. digital input voltage 5.0 4.0 3.0 2.0 0 06803-038 output voltage (v) time (s) 1.0 4.5 3.5 2.5 1.5 0.5 v dd = 5 v , v ref = 4.096v t a = 25oc 1/4 scale t o 3/4 scale 3/4 scale t o 1/4 scale output loaded with 5k? and 200pf t o gnd 0 2 4 6 8 10 12 14 figure 27 . settling time 06803-039 ch1 2v ch3 2v m2ms a ch1 2.52v 3 1 t 20.4% v ref = 4.096v t a = 25c v dd dac a figure 28 . power - on reset to 0 v 06803-040 ch1 2v ch3 2v m2ms a ch1 2.52v 3 1 t 20.4% v ref = 4.096v t a = 25c output unloaded v dd dac a figure 29 . power - on reset to midscale 06803-041 ch1 5v ch2 500mv m2s a ch2 1.2v 2 1 t 55% ch1 = sclk ch2 = v out v dd = 5v power-up to midscale output unloaded figure 30 . exiting power - down to midscale 6 3 1 ?1 ?3 0 2.5 5.0 7.5 10.0 06803-042 glitch amplitude (mv) time (s) 5 4 2 ?2 0 vdd = 5v v ref = 4.096v t a = 25c code = 0x8000 to 0x7fff output unloaded with 5k ? and 200pf figure 31 . digital -to- analog glitch impulse
ad5024/ad5044/ad5064 data sheet rev. f | page 14 of 28 7 4 1 ?1 ?4 0 2.5 5.0 7.5 10.0 06803-043 glitch amplitude (mv) time (s) 5 6 3 2 0 ?2 ?3 v dd = 5 v , v ref = 4.096v t a = 25oc figure 32 . analog crosstalk 7 4 1 ?1 ?4 0 2.5 5.0 7.5 10.0 06803-044 glitch amplitude (mv) time (s) 5 6 3 2 0 ?2 ?3 v dd = 5v, v ref = 4.096v t a = 25c figure 33 . dac -to- dac crosstalk 06803-045 4s/div 1v/div v dd = 5v, v ref = 4.096v t a = 25oc dac loaded with midscale figure 34 . 0.1 hz to 10 hz output noise plot 0 ?20 ?50 ?80 ?100 5 10 30 40 55 06803-046 v out level (db) frequency (khz) ?90 ?70 ?60 ?10 ?30 ?40 20 50 v dd = 5v, t a = 25oc dac loaded with midscale v ref = 3.0v 200mv p-p figure 35 . total harmonic distortion 24 20 14 8 4 0 1 5 7 10 06803-047 settling time (s) capacitance (nf) 6 10 12 22 18 16 3 9 2 4 6 8 v dd = 5v, v ref = 3.0v t a = 25 c 1/4 scale to 3/4 scale within 1lsb figure 36 . settling time vs. capacitive load 06803-048 ch1 5v ch2 2v m2s a ch1 2.5v 2 1 t 1 1% v dd = 5v v ref = 4.096v t a = 25oc dac a clr figure 37 . hardware clr
data sheet ad5024/ad5044/ad5064 rev. f | page 15 of 28 10 0 ?10 ?20 ?60 10 100 1000 10000 06803-049 attenuation (db) frequency (khz) ?30 ?40 ?50 ch a ch b ch c ch d 3db point figure 38. multiplying bandwidth 5.0 4.0 3.0 2.0 0 06803-050 output voltage (v) time ( s) 1.0 4.5 3.5 2.5 1.5 0.5 v dd = 5v, v ref = 4.096v t a = 25c 1/4 scale to 3/4 scale 3/4 scale to 1/4 scale output loaded with 5k ? and 200pf to gnd 0 2 4 6 8 10 12 14 figure 39. typical output slew rate 0.0010 0.0008 0.0006 0.0004 0.0002 0 ?0.0002 ?0.0004 ?0.0006 ?0.0008 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 06803-051 ? voltage (v) current (ma) code = midscale v dd = 5v, v ref = 4.096v figure 40. typical output load regulation 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 06803-052 ? v out (v) i out (ma) code = midscale v dd = 5v, v ref = 4.096v figure 41. typical current limiting plot 06803-053 ch1 50mv ch2 5v m4s a ch2 1.2v t 8.6% dac a 295mv p-p t a = 25c v dd = 5v, v ref = 4.096v figure 42. glitch upon entering power-down (1 k to gnd) from zero scale, no load 06803-054 ch1 50mv ch2 5v m4s a ch2 1.2v t 8.6% dac a 200mv p-p t a = 25c v dd = 5v, v ref = 4.096v sclk figure 43. glitch upon entering power-down (1 k to gnd) from zero scale, 5 k/200 pf load
ad5024/ad5044/ad5064 data sheet rev. f | page 16 of 28 06803-055 ch1 20mv ch2 5v m4s a ch2 1.2v t 8.6% dac a 129mv p-p v dd = 5v,v ref = 4.096v t a = 25c sclk figure 44 . glitch upon exiting po wer - down (1 k? to gnd) to zero scale, no load 06803-056 ch1 20mv ch2 5v m4s a ch2 1.2v t 8.6% dac a 170mv p-p sclk t a = 25c v dd = 5v, v ref = 4.096v figure 45 . glitch upon exiting power - down (1 k? to gnd) to zero scale, 5 k ? /200 pf load
data sheet ad5024/ad5044/ad5064 rev. f | page 17 of 28 terminology relative accuracy (inl) for the dac, relative accuracy, or integral n onlinearity (inl), is a measure of the maximum deviation in lsbs from a straight line passing through the endpoints of the dac transfer function . figure 8 , figure 9 , and figure 10 show plots of typical inl vs. code. differential nonlinearity (dnl) dnl is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monoto - nic ity. this dac is guaranteed mono tonic by design. figure 11, figure 12 , and figure 13 show plots of typical dnl vs. code. offset error offset error is a measure of the difference between the actual v out and the ideal v out , expressed in millivolts in the linear region of the transfer function. offset error is calculated using a reduced code range ad5064/ad5604 - 1: code 512 to code 65,024; ad5044: code 128 to code 16,256; ad5024: code 32 to code 4064, with output unloaded . offset error can be negative or positive and is expressed in millivolts. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal, expressed as a percentage of the full - scale range. offset error temperature coefficient offset error temperature coefficient is a measure of the change in offset error with a change in temperature. it is expressed in microvolts per degree celsius. g ain temperature coefficient gain error drift is a measure of the change in gain error with changes in temperature. it is expressed in parts per million of full - scale range per degree celsius. full - scale error full - scale error is a measure of the output err or when full - scale code (0xffff) is loaded into the dac register. ideally, the output should be v ref ? 1 lsb. full - scale error is expressed as a percentage of the full - scale range. measured with v ref < v dd . digital -to - analog glitch impulse digital - to - analog glitch impulse is the impulse injected into the analog output when the input code in the dac regis ter changes state. it is normally specified as the area of the glitch in nanovolt - seconds and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x7fff to 0x8000). see figure 31. dc power supply rejection ratio (psrr) psrr indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full - scale output of the dac. it is measured in decibels. v ref is held at 2. 5 v, a n d v dd is varied by 10%. measured with v ref < v dd . dc crosstalk dc crosstalk is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full - scale output change on one dac (or soft pow er - down and power - up) while monitoring another dac kept at midscale. it is expressed in microvolts. dc crosstalk due to load current change is a measure of the impact that a change in load current on one dac has to another dac kept at midscale. it is expressed in microvolts per milliamp. reference feedthrough reference feedthrough is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated (that is, ldac is high). it is expr essed in decibels. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from the digital input pins of the device, but it is measured when the dac is not being written to ( sync held high). it is specified in nanovolt - seconds and measured with one simultaneous data and clock pulse loaded to the dac. digital crosstalk digital crosstalk is the glitch impulse transferred to the output of one dac at midscale in response to a full - scale code change (all 0s to all 1s or vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in nanovolt - seconds. analog crosstalk analog crosstalk is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input registers with a full - scale code change (all 0s to all 1s or vice versa) while keeping ldac high, and then pulsing ldac low and monitoring the output of the dac whose digital code has not changed. the area of the glitch is expressed in nanovolt -seconds.
ad5024/ad5044/ad5064 data sheet rev. f | page 18 of 28 dac -to - dac crosstalk dac - to - dac crosstalk is the glitch impulse transferred to the output of one dac due to a digital code change and subse quent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full - scale code change (all 0s to all 1s or vice versa) with ldac low and monitoring the output of anoth er dac. the energy of the glitch is expressed in nanovolt - seconds. multiplying bandwidth the multiplying bandwidth is a measure of the finite bandwidth of the amplifiers within the dac. a sine wave on the reference (with full - scale code loaded to the dac) appears on the output. the multiplying bandwidth, expressed in kilohertz, is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) total harmonic distortion is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonics present on the dac output. it is measured in decibels.
data sheet ad5024/ad5044/ad5064 rev. f | page 19 of 28 theory of operation digital - to - analog converter the ad5024/ad5 044/ad5064/ad5064 - 1 are single 12 - /14 -/ 16- bit, serial input, voltage output dacs with an individual reference pin. the ad5064 - 1 model (see the ordering guide ) is a 16 - bit, serial input, voltage output dac that is identical to o ther ad5064 models but with a single reference pin for all dacs. the parts operate from supply voltages of 4.5 v to 5.5 v. data is written to the ad5024/ad5044/ad5064/ad5064 -1 in a 32- bit word format via a 3 - wire serial interface. the ad5024/ ad5044/ad5064/ad5064 - 1 incorporate a power - on reset circuit that ensures that the dac output powers up to a known output state. the devices also have a software power - down mode that reduces the typical current consumption to typically 400 na. because the input coding t o the dac is straight binary, the ideal output voltage when using an external reference is given by ? ? ? ? ? ? = n refin out d vv 2 where: d is the decimal equivalent of the binary code that is loaded to the dac register (0 to 65,535 for the 16 - bit ad5064). n is the dac resolution. dac architecture the dac architecture of the ad5064 consists of two matched dac sections . a simplified circuit diagram is shown in figure 46. the four msbs of the 16 - bit data word are decoded to drive 15 swit ches, e1 to e15. each of these switches connects one of 15 matched resistors to either gnd or the v ref buffer output. the remaining 12 bits of the data - word drive the s0 to s11 switches of a 12 - bit voltage mode r - 2r ladder network. 2r s0 v ref 2r s1 2r s11 2r e1 2r e2 2r e15 2r v out 12-bit r-2r ladder four msbs decoded in to 15 equa l segments 06803-006 figure 46 . dac ladder structure reference buffer the ad5024/ad5044/ad5064/ad5064 - 1 operate with an exter - nal reference. for most models, e ach dac has a dedicated voltage reference pin. the ad5064 - 1 model has a single voltage reference pin for all dacs. the reference input pin has an input range of 2.2 v to v dd . this input voltage is then buffered internally to provide a reference for the dac core. output amplifier the output buffer amplifier can generate rail - to - rail voltages on its output, which gives an output range of 0 v to v dd . the amplifier is capable of driving a load of 5 k? in parallel with 200 pf to gnd. the slew rate is 1.5 v/s with a ? to ? scale settling time of 5.8 s. serial interface the ad5024/ad5044/ad5064/ad5064 - 1 have a 3 - wire seri al interface ( sync , sclk, and din) that is compatible with spi, qspi, and microwire interface standards as well as most dsps. see figure 4 for a timing diagram of a typical write sequence. the ad5064 - 1 model con tains an sdo pin to allow the user to daisy - chain multiple devices together (see the daisy - chaining section). shift register the ad5024/ad5044/ad5064/ad5064 - 1 shift register is 32 bits wide. the first four bits are dont cares. t he next four bits are the com mand bits, c3 to c0 (see table 8 ), followed by the 4 - bit dac address bits, a3 to a0 (see table 9 ), and finally the bit data - word. the data - word comprises 12 - bit, 14 - bit, or 16 - bit input code, followed by eight, six, or four dont care bits for the ad5024, ad5044, and ad5064/ad5064 - 1, respectively (see figure 47, figure 48 , and figure 49 ). these data bits are transferred to the dac register on the 32 nd falling edge of sclk. commands can be executed on individually selected dac channels or on all dacs. table 8 . command definitions command c3 c2 c1 c0 description 0 0 0 0 write to input register n 0 0 0 1 update dac register n 0 0 1 0 write to input register n, update all (software ldac ) 0 0 1 1 write to and update dac channel n 0 1 0 0 power down/power up dac 0 1 0 1 load clear code register 0 1 1 0 load ldac register 0 1 1 1 reset (power - on reset) 1 0 0 0 set up dcen register 1 (daisy - chain enable) 1 0 0 1 reserved 1 1 1 1 reserved 1 available in the ad5064 - 1 14- lead tssop package only. table 9 . addre ss commands address (n) selected dac channel a3 a2 a1 a0 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d 1 1 1 1 all dacs
ad5024/ad5044/ad5064 data sheet rev. f | page 20 of 28 address bits command bits c3 c2 c1 c0 a3 a2 a1 a0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x x x x x db31 (msb) db0 (lsb) data bits 06803-009 figure 47 . ad5024 shift register content address bits command bits c3 c2 c1 c0 a3 a2 a1 a0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x x x db31 (msb) db0 (lsb) dat a bits 06803-008 figure 48 . ad5044 sh ift register content address bits command bits c3 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x db31 (msb) db0 (lsb) dat a bits 06803-007 figure 49 . ad5064/ad5064 - 1 shift register content sclk din db31 db0 invalid write sequence: sync high before 32 nd falling edge valid write sequence, output updates on the 32 nd falling edge db31 db0 sync 06803-010 figure 50 . sync interrupt facility
data sheet ad5024/ad5044/ad5064 rev. f | page 21 of 28 modes of operation there are three main modes of operation: standal one mode where a single device is used, daisy - chain mode for a system that contains several dacs, and power - down mode when the supply current falls to 0.4 a at 5 v. standalone mode the write sequence begins by bringing the sync line low. data from the din line is clocked into the 32 - bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 50 mhz, making the ad5024/ad5044/ad5064/ad5064 - 1 compatible with high speed dsps. on the 32 nd falling clock edge, th e last data bit is clocked in and the programmed function is executed, that is, an ldac - dependent change in dac register contents and/or a change in the mode of operation. at this stage, the sync line can be kept low or be brought high. in either case, it must be brought high for a minimum of 3 s (single channel, see table 4 , t 8 parameter) before the next write sequence so that a falling edge of sync can initiate the next writ e sequence. sync should be idled at rails between write sequences for even lower power operation of the part. sync interrupt in a normal write sequence, the sync line is kept low for at least 32 fallin g edges of sclk, and the dac is updated on the 32 nd falling edge. however, if sync is brought high before the 32 nd falling edge, this acts as an interrupt to the write sequence. the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the operating mode occurs (see figure 50). daisy-chaining for systems that contain several dacs the sdo pin can be used to daisy - chain several devices together and provide serial readbac k. the daisy - chain mode is enabled through a software executable daisy - chain enable (dcen) command. command 1000 is reserved for this dcen function (see table 8 ). the daisy - chain mode is enabled by setting bit db1 in the dcen reg ister. the default setting is standalone mode, where db1 = 0. table 10 shows how the state of the bit corresponds to the mode of operation of the device. table 10 . dcen (daisy - chain enable) register d b1 db0 description 0 x standalone mode (default) 1 x dcen mode the sclk is continuously applied to the shift register when sync is low. if more than 32 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting this line to the din input on the next dac in the chain, a daisy - chain interface is constructed. each dac in the system requires 32 cloc k pulses; therefore, the total number of clock cycles must equal 32n, where n is the total number of devices that are updated. if sync is taken high at a clock that is not a multiple of 32, it is considered an invalid frame and the d ata is discarded. when the serial transfer to all devices is complete, sync is taken high. this prevents any further data from being clocked into the shift register. in daisy - chain mode, the ldac pin cannot be ti ed permanently low. the ldac pin must be used in asynchronous ldac update mode, as shown in figure 5 . the ldac pin must be brought high after pulsing. this allows all dac outp uts to simulta - neously update. the serial clock can be continuous or a gated clock. a continuous sclk source can be used only if sync can be held low for the correct number of clock cycles. in gated clock mode, a burst clock containi ng the exact number of clock cycles must be used, and sync must be taken high after the final clock to latch the data. table 11 . 32- bit shift register contents for daisy - chain enable msb lsb db3 1 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 to db2 db1 db0 x 1 0 0 0 x x x x x 1/0 x dont cares command bits (c3 to c0) address bits (a3 to a0) dont cares dcen register
ad5024/ad5044/ad5064 data sheet rev. f | page 22 of 28 power - on reset the ad5024/ad5044/ad5064/ad5064 - 1 contain a power - on r eset circuit that initializes the registers to their default values and controls the output voltage during power - up. by connecting the por pin low, the ad5024/ad5044/ad5064/ad5064 - 1 output powers up to zero scale. note that this is outside the linear regio n of the dac; by connecting the por pin high, the ad5024/ad5044/ad5064/ad5064 -1 output powers up to midscale. the output remains powered up at this level until a valid write sequence is made to the dac. this is useful in applications where it is important to know the state of the output of the dac while it is in the process of powering up. there is also a software executable reset function that resets the dac to the power - on reset code. command 0111 is designated for this reset function (see table 8 ). any events on ldac or clr during power - on reset are ignored. the power - on reset circuit is triggered when v dd passes 2.6 v approximately and takes 50 s to complete. no writes to the ad5024/ad5044/ ad5064/ad5064 - 1 should take place during this time. for applications which have a slow v dd ramp time (for example , more than 2 ms to 3ms) , it is recommended that a software reset command is written when the power supplies have reached their final value. power - down modes the ad5024/ad5044/ad5064/ad5064 - 1 contain three separate power - down modes. command 0100 is designated for the power - down function (see table 8 ). these power - down modes are software - programmable by setting two bit s, bit db9 and bit db8, in the shift register. table 12 shows how the state of the bits corresponds to the mode of operation of the device. table 12 . modes of operation db9 db8 operating mode 0 0 norm al operation power - down modes: 0 1 1 k ? to gnd 1 0 100 k ? to gnd 1 1 three - state any or all dacs (dac d to dac a) can be powered down to the selected mode by setting the corresponding four bits (db3, db2, db1, db0) to 1. see table 13 for the contents of the shift register during power - down/power - up operation. when both bit db9 and bit d8 in the shift register are set to 0, the part works normally with its normal power consumption of 4 ma at 5 v. however, for the three power - down modes, the supply current falls to 0.4 a at 5 v. not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values . this has the advantage that the output impedance of the part is known while the part is in power - down mode. there are three different power - down options. the output is connected inter - nally to gnd through either a 1 k? or a 100 k? resistor, or it is left open - circuited (three - state). the output stage is illustrated in figure 51. resist or network v out dac power-down circuit ry amplifier 06803-011 figure 51 . output stage during power - down the bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when the power - down mode is activated. however, the conten ts of the dac register are unaffected when in power - down. the dac register can be updated while the device is in power - down mode. the time to exit power - down is typically 4.5 s for v dd = 5 v (see figure 30 ). table 13 . 32- bit shift register contents for power - up/power - down function msb lsb db31 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 to db10 db9 db8 db7 to db4 db3 db2 db1 db0 x 0 1 0 0 x x x x x pd1 pd0 x dac d dac c dac b d ac a dont cares command bits (c3 to c0) address bits (a3 to a0) dont cares dont cares power - down mode dont cares power - down/power - up channel selection set bit to 1 to select
data sheet ad5024/ad5044/ad5064 rev. f | page 23 of 28 clear code register the ad5024/ad5044/ad5064/ad5064 - 1 have a hardware clr pin that is an asynchronous clear input. the clr input is falling edge sensitive. bringing the clr line low clears the contents of the input register and the dac registers to the data contained in th e user -configurable clr register and sets the analog outputs accordingly (see table 14 ). this function can be used in system calibration or reset to load zero scale, midscale, or full scale to all channels toget her. note that zero scale and full scale are outside the linear region of the dac. these clear code values are user - programmable by setting two bits, bit db1 and bit db0, in the shift register (see table 14 ). the default setting clears the outputs to 0 v. command 0101 is designated for loading the clear code register (see table 8 ). table 14 . clear code register db1 (cr1) db0 (cr0) clears to code 0 0 0x0000 0 1 0x8000 1 0 0xffff 1 1 no operation the part exits clear code mode on the 32 nd falling edge of the next write to the part. if hardware clr pin is activated during a write sequence, the write is aborted. the clr pulse activation time, which is the falling edge of clr to when the output starts to change, is typically 10.6 s. see table 16 for contents of the shift register while loading the clear code register. ldac function hardware ldac pin the outputs of all dacs can be updated simultaneously using the hardw are ldac pin, as shown in figure 4 . ldac can be permanently low or pulsed. there are two methods of using the hardware ldac pin, synchronously and asynchronously. synchronous ldac : after new data is read, the dac registers are updated on the falling edge of the 32 nd sclk pulse, provided ldac is held low. asynchronous ldac : the outputs are not updated at the same time that the input registers are written to. when ldac is pulsed low, the dac registers are updated with the contents of the input registers. software ldac function alternatively, the outputs of all dacs can be updated simulta - neo usly or individually using the software ldac function by writing to input register n and updating all dac registers. command 0010 is reserved for this software ldac function. writing to the dac using command 0110 loads t he 4 - bit ldac register (db3 to db0). the default for each channel is 0; that is, the ldac pin works normally. setting the bits to 1 updates the dac channel regardless of the state of the hardware ldac pin, so that it effectively sees the hardware ldac pin as being tied low (see table 15 for the ldac register mode of operation.) this flexibility is useful in applications where the us er wants to simul taneously update select channels while the remainder of the channels are synchronously updating. table 15. ldac overwrite definition load ldac register ldac bits (db3 to db0) ldac pin ldac operation 0 1 or 0 determined by the ldac pin. 1 x 1 dac channels update, overrides the ldac pin. dac channels see ldac as 0. 1 x = dont care . the ldac register gives the user extra flexibility and control over the hardware ldac pin (see table 17 ). setting the ldac bits (db0 to db3) to 0 for a dac channel means tha t this channels update is controlled by the hardware ldac pin. table 16 . 32- bit shift register contents for clear code function msb lsb db31 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 to db 2 db1 db0 x 0 1 0 1 x x x x x 1/0 1/0 dont cares command bits (c3 to c0) address bits (a3 to a0) dont cares clear code register (cr1 to cr0) table 17 . 32- bit shift register contents for ldac overwrite function msb lsb db31 to db28 db27 db26 db25 db24 db23 db22 db21 db20 db19 to db4 db3 db2 db1 db0 x 0 1 1 0 x x x x x dac d dac c dac b dac a dont cares command bits (c3 to c0) address bits (a3 to a0) dont cares dont cares setting ldac bits to 1 overrides ldac pin
ad5024/ad5044/ad5064 data sheet rev. f | page 24 of 28 power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit boar d (pcb) containing the ad5024/ad5044/ ad5064/ad5064 - 1 should have separate analog and digital sections. if the ad5024/ad5044/ad5064/ad5064 - 1 are in a system where other devices require an agnd - to - dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5024/ad5044/ad5064/ad5064 - 1. the power supply to the ad5024/ad5044/ad5064/ad5064 - 1 should be bypassed with 10 f and 0.1 f capacitors. the capaci - tors should be as physically close as possibl e to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor have low effective series resistance (esr) and low effective series inductance (esi), such as is typical of common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals, if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout technique is the microstrip tech - nique, where the component side of the boa rd i s dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a 2 - layer board.
data sheet ad5024/ad5044/ad5064 rev. f | page 25 of 28 microprocessor inter facing ad5024/ad5044/ad5064/ad5064 - 1 to blackfin adsp - bf53x interface figure 52 shows a serial interface betwee n the ad5024/ad5044/ ad5064/ad5064 - 1 and the blackfin ? adsp - bf53x microproces - sor. the adsp - bf53x processor family incorporates tw o dual - channel synchronous serial ports, sport1 and sport0, for serial and multiprocessor communications. using sport0 to connect to the ad5024/ad5044/ad5064/ad5064 - 1, the setup for the interface is as follows: dt0pri drives the din pin of the ad5024/ad5044/ad5064/ad5064 - 1, and tsclk0 drives the sclk of the parts. the sync pin is driven from tfs0. ad5024/ ad5044/ ad5064/ ad5064-1 * adsp-bf53x* *additional pins omitted for clarity. sync tfs0 din dt0pri sclk tsclk0 06803-012 figure 52 . ad5024/ad5044/ad5064/ad5064 - 1 to blackfin adsp - bf53x interface ad5024/ad5044/ad5064/ad5064 - 1 to 68hc1 1/68l11 interface figure 53 shows a serial interface b etween the ad5024/ad5044/ ad5064/ad5064 - 1 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad5024/ ad5044/ad5064/ad5064 - 1, and the mosi out put drives the serial data line of the dac. ad5024/ ad5044/ ad5064/ ad5064-1 * 68hc11/68l11* *additional pins omitted for clarity. sync pc7 sclk sck din mosi 06803-013 figure 53 . ad5024/ad5044/ad5064/ad5064 - 1 to 68hc11/68l11 interface the sync signal is derived from a port line (pc7). the setup conditions for correct operation o f this interface are as follows: the 68hc11/68l11 is configured with its cpol bit as 0, and its cpha bit as 1. when data is being transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 is configured as descri bed previously, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8 - bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to lo ad data to the ad5024/ad5044/ ad5064, pc7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the dac. pc7 is taken high at the end of this procedure. ad5024/ad5044/ad5064/ad5064 - 1 to 80c51/80l51 int erface figure 54 shows a serial in terface between the ad5024/ad5044/ ad5064/ad5064 - 1 and the 80c51/80l51 microcontroller. the setup for the interface is as follows: txd of the 80c51/80l51 drives sclk of the ad5024/ad5044/ad5064/a d5064 - 1, and rxd drives the serial data line of the part. the sync signal is again derived from a bit - programmable pin on the port. in this case, port line p3.3 is used. when data is to be transmitted to the ad5024/ad5044/ad5064/ad5064 - 1, p3.3 is taken low. the 80c51/80l51 transmit data in 8 - bit bytes only; thus, only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitte d, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 output the serial data in a format that has the lsb first. the ad5024/ad5044/ad5064/ad5064 - 1 must receive data with the msb first. the 80c51/80l51 transmit routine should take this into account. ad5024/ ad5044/ ad5064/ ad5064-1 * *additional pins omitted for clarity. din rxd sync p3.3 80c51/80l51* sclk txd 06803-014 figure 54 . ad5024/ad5044/ad5064/ad5064 - 1 to 80c512/80l51 interface ad5024/ad5044/ad5064/ad5064 - 1 to microwire interface figure 55 shows an i nterface between the ad5024/ad5044/ ad5064/ad5064 - 1 and any microwire - compatible device. serial data is shifted out on the falling edge of the serial clock and is clocked into the ad5024/ad5044/ad5064/ad5064 -1 on the rising edge of the sclk. ad5024/ ad5044/ ad5064/ ad5064-1 * *additional pins omitted for clarity. sclk so sync cs microwire* din sk 06803-015 figure 55 . ad5024/ad5044/ad5064/ad5064 - 1 to microwire interface
ad5024/ad5044/ad5064 data sheet rev. f | page 26 of 28 applications informa tion using a reference as a power supply because the supply current required by the ad5024/ad5044/ ad5064/ad5064 - 1 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the parts (see figure 56 ). this is especially useful if the power supply is quite noisy or if the system supply voltages are at some value other than 5 v (for exampl e, 15 v). the voltage reference outputs a steady supply voltage for the ad5024/ad5044/ad5064/ ad5064 -1 . if the low dropout ref195 is used, it must supply 3 ma of current to the ad5024/ad5044/ad5064/ad5064 -1, wit h no load on the output of the dac. when the dac output is loaded, the ref195 also needs to supply the current to the load. the total current required (with a 5 k? load on the dac output) is 3 ma + (5 v/5 k?) = 4 ma the load regulation of the ref195 is typically 2 ppm/ma, which results in a 3 ppm (15 v) error for the 4 ma current drawn from it. this corresponds to a 0.196 lsb error. sync sclk din 15v 5v v out = 0v to 5v v dd ref195 ad5024/ ad5044/ ad5064/ ad5064-1 3-wire serial interface 06803-016 figure 56 . ref195 as power supply to the ad5024/ad5044/ad5064/ad5064 -1 bipolar operation the ad5024/ad5044/ad5064/ad5064 - 1 have been designed for single - supply operation, but a bipolar output range is also possible using t he circuit shown in figure 57 . the circuit gives an output voltage range of 5 v. r a i l - to - rail operation at the amplifier output is achievable using an ad8638 or an ad8639 as the output amplifier. assuming v dd = v ref , the output voltage for any input code can be calculated as follows: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? = r1 r2 v r1 r2r1d vv dd dd out 536,65 where d represents the input code in decimal (0 to 65,535). with v dd = 5 v, r1 = r2 = 10 k?, v5 536,65 10 ? ? ? ? ? ? ? = d v out this is an output voltage range of 5 v, with 0x0000 corre - sponding to a ?5 v output, and 0xffff corresponding to a +5 v output. 06803-017 3-wire serial interface 5 n? +5v +5v ad5024/ ad5044/ ad5064/ ad5064-1 v dd v outa 5 n? 5v 0.1f 10f v refa ?5v 5v v ref ad8638/ ad8639 figure 57 . bipolar operation using the ad5024/ad5 044/ad5064/ad5064 - 1 with a galvanically isolated interface in process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common - mode voltages that can occur in the area where the dac is functioning. i coupler? provides isolation in excess of 2.5 kv. the ad5024/ad5044/ad5064/ad5064 - 1 use a 3- wire serial logic interface, so the adum1300 three - channel digital isolator provides the required isolation (se e figure 58 ). the power supply to the part also needs to be isolated, which is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5024/ ad5044/ad5064/ad5064 -1. 0.1f gnd din sync sclk power 10f sdi sclk data ad5024/ ad5044/ ad5064/ ad5064-1 v out x v ob v oa v oc v dd v ic v ib v ia adum1300 5v regulator 06803-018 figure 58 . ad5024/ad5044/ad5064/ad5064 - 1 with a galvanically isolated interface
data sheet ad5024/ad5044/ad5064 rev. f | page 27 of 28 outline dimensions compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 sea ting plane figure 59 . 14 - lead thin shrink small outline package [tssop] (ru - 14) dimensions shown in millime ters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 60 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters
ad5024/ad5044/ad5064 data sheet rev. f | page 28 of 28 ordering guide model 1 temperature range accuracy resolution package description package option ad5064aruz -1 ? 40c to +125c 4 lsb inl 16 bits 14- lead tssop ru -14 ad5064aruz - 1reel7 ?40c to +125c 4 lsb inl 16 bits 14- lead tssop ru -14 ad5064bruz -1 ?40c to +125c 1 lsb inl 16 bits 14- lead tssop ru -14 ad5064bruz - 1reel7 ?40c to +125c 1 lsb inl 16 bits 14-le ad tssop ru -14 ad5064bruz ?40c to +125c 1 lsb inl 16 bits 16- lead tssop ru -16 ad5064bruz - reel7 ?40c to +125c 1 lsb inl 16 bits 16- lead tssop ru -16 ad5044bruz ?40c to +125c 1 lsb inl 14 bits 16- lead tssop ru -16 ad5044bruz - reel7 ?40c to +125c 1 lsb inl 14 bits 16- lead tssop ru -16 ad5024bruz ?40c to +125c 0.5 lsb inl 12 bits 16- lead tssop ru -16 ad5024bruz - reel7 ?40c to +125c 0.5 lsb inl 12 bits 16- lead tssop ru -16 eval - ad5064- 1ebz 14- lead tssop evaluation board eval - ad5064ebz 16- lead tssop evaluation board 1 z = rohs compliant part. ? 2008 C 2013 a nalog devices, inc. all rights reserved. trademarks and reg istered trademarks are the property of their respective owners. d06803 -0- 6 /13(f )

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